The transmission of Ethernet frames is a relatively complex process, due primarily to the need to implement the Ethernet Medium Access Control functions specified by the IEEE 802.3 standards for Carrier Sense Multiple Access networks. The functions that must be performed during transmission include activity sensing and deference, collision detection and retransmission of frames corrupted by Collisions, flow control, error detection and recovery, and statistics maintenance.
High-speed Ethernet packet switches normally use a purely hardware-based approach to controlling the transmission of frames at the transmit ports of the switching System. This is required because of the high frame rates involved. For example, typical Fast Ethernet packet switches, operating at data rates of too megabits/sec per port, need to process on the order of 150,000 frames per second to support transmission of Ethernet frames at full speed. This implies that a frame transmission needs to be initiated once ever 6.7 microseconds; such rapid frame processing is beyond the capabilities of normal software architectures running on standard low-cost embedded CPUs today. As a result, these packet switches use dedicated, hard-wired logic to handle transmitted frames.
The pure-hardware implementation of the transmit process has several disadvantages. For example, the implementation is far less flexible, as all of the functions must be encoded into hardware; thus it is not possible for the process to be easily modified to take into account future enhancements in areas such as flow control, etc. A hardware implementation may be less cost-effective, as a good deal of the functionality is rarely used, but nevertheless consumes valuable hardware resources. An example of this is the processing required to deal with excessive collisions while transmitting Ethernet packets; the processing is relatively complex, but an excessive collision condition occurs very rarely in properly functioning Ethernet networks. Finally, the expense and inflexibility of the hardware-only implementation is multiplied when the packet switch has to deal with frames that require special processing (for example, signaling frames used by higher-level protocols that must be transmitted in the normal fashion as well as copied to internal packet buffers for use by the switch management entity); the recognition and special handling of such frames requires a good deal of resources when implemented solely in hardware.
Thus, the high packet transmission rates of modern packet switches virtually mandate the need for dedicated hardware to perform the various complex functions required in the transmit path of Ethernet switching equipment. When these functions are implemented in pure hardware, however, the advantages of software (namely, flexibility and low cost coupled with the ability to realize very complex processing) are lost. The resulting implementation is expensive, difficult to extend and modify, and complex to design.
The object of the invention is to obviate the disadvantages of a hardware-only implementation of a transmit datapath for a Fast Ethernet packet switch by using a combination of hardware and firmware (i.e., a embedded CPU). It is a further object of the invention to introduce a firmware function at the appropriate point in the packet transfer path to allow the complex and infrequent functions to be implemented in firmware for flexibility and low cost, while performing the simple and repetitive functions in hardware for speed.